A state of the art technology for the future

Murata's 3D MEMS is a technology that is based on the toolset and processes for manufacturing semiconductor devices. It means that all manufacturing operations are performed on silicon wafers containing thousands of devices. This ensures a similar scale of economy as with semiconductor integrated circuits. The use of silicon as the raw material, deposition of thin films and patterning by photolithographic means are similar to circuits. However, since sensing the three dimensional world requires three dimensional sensors, some specific tools and processes have been added to the 3D MEMS toolbox.

Mechanical sensors are based on springs, inertial bodies and sensing capacitors. In 3D MEMS these are etched out of the silicon wafer using etching processes specific to the MEMS industry. Since the 1970s wet chemical etching of silicon in alkaline etchants has been used. This method produces a crystal direction dependent anisotropy of etch speed that enables precise control of dimensions. This traditional etching has been superseded by a dry etching method: deep reactive ion etching or DRIE. This offers anisotropy based on direction of the ion flux normal to the wafer surface. DRIE enables much more design freedom and a higher density of structures than wet etching and is the chosen technology for gyros and multi-axis accelerometers.

For precise control of the etching process in the vertical direction and electrical isolation of the silicon structures, an isolation layer beneath the active structures is required. For this purpose Murata Electronics Oy uses silicon on insulator (SOI) and silicon on insulator and cavities (CSOI) wafers. These wafers allow good control of the vertical dimensions of the 3D MEMS structures, a high degree of design freedom of the in-plane shape of the structures and good isolation with low parasitic capacitances between them.

Integrated circuits are passivated from environmental influences by deposited layers of selected materials on the top of the wafer. This is not possible with MEMS since the structures need to remain movable. In MEMS the passivation is achieved by bonding a second wafer to the MEMS wafer. This wafer is called the cap or the capping wafer. We are the pioneer in producing capping wafers with extremely tight dimensional control and low parasitic loads to the small capacitive signals. The capping wafers are based on proprietary technology for heterogeneous glass-silicon structures. Our capping wafers offer up to tens of electrical vias vertically through the wafer with extremely good isolation and low parasitics. Due to tight dimensional control, our capping wafer also offers electrodes for vertical capacitive detection.

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